Senior Staff Test Engineering Lead

THE ROLE: The Technical Lead is responsible for the test solution for a next-generation AMD Products. This position serves as the Test Engineering team's Technical Leader and go-to expert for solutions. This position requires engagement with Product, Design, Platform Engineering, Device Analysis, Foundry, Quality and Reliability Engineering to drive test and characterization plan, 1st silicon bring-up, silicon debug, attainment and optimization of yield and performance distributions, test costs and product quality for next-generation AMD products. This role offers opportunities for experienced Engineers who are interested in growing their technical scope over time , based on individual performance and business needs. THE PERSON: We are looking for one with a passion for technical development, possessing broad technical leadership, critical problem solving and troubleshooting skills. The person must be a team player and have good and effective communications to deep dive into technical discussion with other members across the globe and use data to illustrate their points. This person is expected to be independent, self-starter, well organized and have the sense of responsibility to see projects through beginning to the end as well as the ability to lead by influence. This person is expected to be market savvy and comfortable in a multi-tasking environment. KEY RESPONSIBILITIES: New Product Introduction (NPI) • Define and drive pre silicon test and characterization strategies for complex SoC products. • Establish DFT and pattern requirements, and work with Design and Verification teams to ensure test readiness prior to first silicon. • Lead first silicon bring up, silicon debug, and characterization execution across PVT corners. • Analyze yield, performance distributions, and device failures; lead root cause analysis and drive corrective actions across global teams. • Perform circuit sensitivity analysis, interpret findings, and guide deep dive investigations to resolution. • Drive innovation in SoC test, debug, DFT, and test methodology, translating ideas into production ready solutions. Production & Cost Optimization • Own test content optimization to meet product quality and cost targets. • Drive yield, test time, and margin improvements from wafer sort through backend test. • Partner with manufacturing and quality teams to ensure stable, scalable production. PREFERRED EXPERIENCE: Technical • Strong hands-on experience supporting complex SoC products (e.g., mobile or automotive processing units) . • Proven technical leadership across at least one full SoC product lifecycle (pre silicon to production). • Deep expertise in DFT and ATE test methodologies , spanning areas like ATPG Scan, MBIST, Functional, and High‑Speed IO testing across complex SoC environments. • Strong experience with Advantest 93k/Teradyne test platforms. • Solid understanding of CPU / GPU / SoC architectures with system level interactions as a plus. • Strong programming or scripting skills (Python, C/C++, Perl, Java). • Experience with industry EDA tools (Mentor, Synopsys, Cadence) is a plus. Leadership • Demonstrated ability to act as a technical decision‑maker and mentor within the test organization. • Strong communication skills to engage deeply with global, cross‑functional engineering teams. • Willingness and capability to take on broader ownership, including mentoring engineers and contributing to long‑term test strategy and team development. • Strong ability to lead by influence. • Ability to program manage and drive test schedules and deliverables ACADEMIC CREDENTIALS: • Bachelor's/Master's in Electrical/Electronic Engineering.