Physical Design Engineer / Senior Physical Design Engineer

Responsibility • Responsible for high-performance block implementation (RTL to GDSII). • Perform block level floor planning, power grid implementation, APR placement, timing optimisation, CTS and routing. • Close the design to meet timing, power budget and area targets. • Run physical verification flows (DRC/LVS/EM/IR), and implement fixes to meet the requirements. • Implement ECO’s to address functional bugs, timing and physical verification violations. • Responsible for the generation and maintenance of block-level STA constraints and performing STA signoff checks. • Responsible for timing model generation and supporting the successful integration of blocks into SOC. Qualification • At least 3 years of hands-on experience in digital-physical design. • Master’s/Bachelor’s degree in Electrical Engineering with an emphasis in IC design， master's degree preferred. • Experience with digital Physical design and Static Timing Analysis • Experience in floor planning and routing. • Experience in advanced process nodes. • Good experience with Synopsys implementation tools (DC, ICC2), and experience with Cadence (Innovus) implementation tool is a plus. • Experience in Mentor Verification tool, Calibre. • Proficient in TCL coding, Perl/Python knowledge is a plus. • Good written and communication skills. • Bilingual to communicate with associates in China is preferable.