Senior AI Engineer – Design Automation

Description: Apply advanced AI techniques to accelerate the design of faster, smaller, and more power-efficient chips. Key Responsibilities: - Harness Large Language Models (LLMs) to automatically generate, refine, and debug RTL code in Verilog/SystemVerilog. - Apply Graph Neural Networks (GNNs) to analyze chip netlists and predict wiring, spacing, and other physical design issues early in the flow. - Develop autonomous AI agents capable of driving EDA tools, interpreting results, diagnosing failures, and applying fixes with minimal human intervention. - Translate cutting-edge academic research in AI for EDA into robust, production-ready software tools used by silicon engineering teams. Requirements: - Ph.D. in Computer Science, Artificial Intelligence, Machine Learning, or related field - ‎Research (thesis or publications) related to Graph Machine Learning, Verilog/SystemVerilog optimization, or NLP techniques applied to code/hardware description languages. - Knowledge in traditional VLSI design flows, including synthesis, static timing analysis, and physical design with be a plus - Strong proficiency with PyTorch, PyTorch Geometric (PyG), and modern LLM frameworks. - Programming skills in Python.