Junior FPGA Engineer

DRW is a diversified trading firm with over 3 decades of experience bringing sophisticated technology and exceptional people together to operate in markets around the world. We value autonomy and the ability to quickly pivot to capture opportunities, so we operate using our own capital and trading at our own risk. Headquartered in Chicago with offices throughout the U.S., Canada, Europe, and Asia, we trade a variety of asset classes including Fixed Income, ETFs, Equities, FX, Commodities and Energy across all major global markets. We have also leveraged our expertise and technology to expand into three non-traditional strategies: real estate, venture capital and cryptoassets. We operate with respect, curiosity and open minds. The people who thrive here share our belief that it’s not just what we do that matters–it's how we do it. DRW is a place of high expectations, integrity, innovation and a willingness to challenge consensus. We’re looking for a Junior or Graduate FPGA Engineer to join our FPGA team supporting trading desks in Asia. This is an entry-level role suited to recent graduates, interns, or engineers with 1–2 years of hands-on experience who want to grow their FPGA design skills in a low-latency, high-throughput environment. You’ll work closely with experienced engineers across software, trading and hardware teams, participate in the full development lifecycle, and gain practical experience in FPGA synthesis, lab bring-up and system testing. What you’ll do • Contribute to the implementation of FPGA applications (RTL development, simulation and verification) under the guidance of senior engineers • Run parts of the FPGA tool flow (synthesis, place & route, static timing analysis) and learn to interpret the results • Help plan and execute system- and block-level testcases and laboratory bring-up of new hardware • Participate in debugging and characterization of boards and FPGA designs; support production incidents with senior team members • Work with software, network and trading teams to integrate FPGA components into broader systems • Research new tools, techniques and FPGA technologies and propose ideas for incremental improvements • Produce clear documentation and test reports Who we’re looking for • Bachelor’s or Master’s or PhD degree in Electrical Engineering, Computer Engineering, Computer Science or a related field (recent/upcoming graduates welcome) • 0–2 years of professional experience, or equivalent experience from internships, research or university projects • Practical experience writing RTL (Verilog or SystemVerilog) — course projects or internship work is fine • Familiarity with FPGA development flows and tools (Xilinx or Intel/Altera) or strong desire to learn them quickly • Basic experience with simulation and verification tools (e.g., ModelSim, Questa, or equivalent) or demonstrable coursework/projects • Comfortable using Linux and basic scripting (Python, Bash) for test automation and tooling • Good problem solving, debugging and communication skills — ability to work collaboratively in cross-functional teams • Eagerness to learn, take feedback, and grow technical ownership over time Nice to have • Exposure to high-speed interfaces (Ethernet/PCIe/DDR memory) or SoC subsystems • Experience with C/C++ for embedded systems or software-hardware integration • Knowledge of networking fundamentals (TCP/IP) or timing/latency optimization concepts • Familiarity with version control (Git) and CI workflows What we offer • Mentorship from experienced FPGA and systems engineers • Hands-on learning on real trading hardware and production systems • Opportunities for rapid responsibility growth and career progression • Collaborative, engineering-driven culture and competitive compensation For more information about DRW's processing activities and our use of job applicants' data, please view our Privacy Notice at https://drw.com/privacy-notice . California residents, please review the California Privacy Notice for information about certain legal rights at https://drw.com/california-privacy-notice . #LI-PR1