Layout Engineer

The descriptions are for layout engineers for our Library Group. Library Group is a part of Central Engineering Group. In Library Group, we focus on circuit design for memory, I/O (Input/Output), and Standard Cells. Requirements: • Strong layout knowledge with a minimum of 3 to 4 years of experience • Skills include Cadence layout, Cadence schematic capture, using CALIBRE & Hercules verification tools. • Strong layout knowledge in submicron process, e.g. 16nm, 7nm, 5nm, 3nm , 2nm , 1.4nm etc • Experienced in digital (standard cell, memory, I/O) layout • Experienced in analog layout is also a plus Job Description: • Responsible to understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout • Schedule time-line & layout floor-planning • Complete quality layout and verification within planned schedule (without supervision for experienced engineer) • Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team Skill Set (Mem): • Strong experience in memory layout design and physical verifications includes LVS, DRC, ERC, Antenna, Electro Migration in CMOS process. • Experienced in Cadence Layout tools VIRTUOSO (XL,VXL or EXL), and CALIBRE verification tools. • Good experience in Floor-planning, hierarchy layout and chip integration. • Knowledge of Script Programming and SKILL Programming would be a plus. • Able to lead or train a team of junior engineers • Good knowledge on memory layout topology. • Experience in memory compiler will be a plus. • Ability to lead on new technology reviews to compile documentation of layout methodology, layout flow and guidelines. • Self-reliant, with ability to work independently as well as a team. • Good leadership quality on project management.