RTL / Digital IC Design Engineer (Junior / Entry-Level)

About the Role Weare seeking a motivated Junior RTL / Digital IC Design Engineer to join our front-end IC design team. In this role, you will contribute to the development of high-speed DSP and digital logic for optical communication systems, working on ASIC/SoC designs that enable next-generation optical interconnects. Key Responsibilities · Develop synthesizable RTL(Verilog/SystemVerilog) for DSP blocks and high-speed datapath logic used in ODSP and photonics ICs. · Translate system and algorithm requirements into RTL micro-architecture including pipelines, datapaths, and control logic. · Perform RTL simulation and debug functionality using testbenches and waveform analysis. · Contribute to high-throughput, low-latency Datapath design with awareness of timing, power, and area constraints. · Collaborate with DV engineers to debug failures and achieve functional coverage closure. · Support synthesis, timing closure, and power optimization with PD teams. · Collaborate with system architects, DSP teams, AMS engineers, and packaging teams for system integration. · Maintain documentation and participate in design reviews. Requirements: · Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or related fields. · 0–2 years of experience in RTL/digital IC design (fresh graduates welcome). · Strong fundamentals in digital design (FSM, pipelines, timing, clocking). · Understanding of ASIC/SoC design flow.