Design Engineer

• Execute the end-to-end physical design flow for complex SoCs and IP blocks (from RTL handoff to GDSII). • Define and drive floorplanning, clock-tree synthesis (CTS), placement, routing, and timing closure strategies. • Own and optimize power, performance, and area (PPA) metrics for assigned designs. • Manage design constraints, synthesis strategies, and sign-off criteria (timing, IR drop, EM, DRC/LVS). • Collaborate with front-end RTL, DFT, verification, and packaging teams to ensure seamless integration. • Drive EDA tool flow automation and methodology enhancements for improved efficiency and scalability. • Mentor and guide junior engineers, fostering technical growth and design excellence. • Work closely with foundries and vendors on process technology bring-up, PDK updates, and tape-out readiness.