Associate Staff Design Engineer

We are seeking a highly skilled Associate Staff Design Engineer to join our Silicon Engineering Team. This role involves leading and hands on various stages of BE implementation flow including, but not limited to, Synthesis, Static Timing Analysis (STA) , Logic Equivalence & Low power checks. You will be responsible for constraints development, timing sign-off of high-performance SoCs and ASICs. You’ll work closely with cross-functional teams to ensure timing closure across various operating modes and process corners. Ideal candidate will have exposure to full gamut of BE cycle – synthesis, Place & route, Logic equivalence, UPF & lowe power checks , STA & PV Signoff and should be able to act as BE lead taking care of full BE implementation cycle of our cutting-edge SoCs through advanced physical design methodologies. PPA optimization and Low power implementation methodologies exposure is a must. Hands-on development, management and validation of timing constraints for RTL-to-GDSII flow in collaboration with Design & DFT teams • Own STA execution for digital blocks and top-level designs • Help in CTS spec generation in collaboration with Design & PnR engineers. • Run Logical Equivalence checks using industry standard tools • Develop low power and UPF development & lowe power checks • Generate and interpret timing reports using industry-standard tools • Implement timing ECOs to resolve critical path issues • Contribute to timing methodology improvements and automation • Perform timing checks for CDC, false paths, and multicycle paths • Lead the team and execute the end-to-end physical design flow for complex SoCs and IP blocks (from RTL handoff to GDSII). • Own and optimize power, performance, and area (PPA) metrics for assigned designs. • Manage design constraints, synthesis strategies, and sign-off criteria (timing, IR drop, EM, DRC/LVS). • Collaborate with front-end RTL, DFT, verification, and packaging teams to ensure seamless integration. Drive EDA tool flow automation and methodology enhancements for improved efficiency and scalability. • Mentor and guide junior engineers, fostering technical growth and design excellence. Must Have Requirements • Bachelor’s or Master’s degree in ECE, EEE, VLSI or related field. • 9-10 years of experience in ASIC physical design • Hands-on expertise in Industry standard EDA tools: Cadence (Genus, Innovus, Tempus, LEC, CLP), or equivalent or Synopsys (ICC2, Fusion Compiler, PrimeTime) • Strong background in synthesis, constraints, margins and timing analysis/fixing. • Knowledge of low-power design techniques (UPF/CPF, power gating, DVFS). • Solid understanding of architecture-to-GDSII flows and sign-off requirements. • Excellent problem-solving and communication skills. Preferred Qualifications • Experience with chip-level integration and hierarchical design methodologies. • Familiarity with DFT, Floor planning, PnR, and physical verification/IR analysis. • Exposure to multi-clock, multi-voltage, and multi-domain designs • Experience of leading small (4-10 members) teams in related domain. • Automation expertise using perl/tcl/tk/python. • Exposure to multi site environment and collaboration.